Breaking the Billion-Gate Barrier

Hardware emulators able to handle one-billion ASIC gates can shorten time to tapeout, improve product quality and eliminate costly re-spins, while reducing software development time ahead of silicon of the most complex SoC ever designed.

As we head into San Francisco for the annual Design Automation Conference (DAC) at the end of this month, the designer community has reason to be enthusiastic about this year’s event. For example, the conference is offering a new User Track where designers will describe their real-world problems and how they solved them. On the Exhibit Floor, designers can see some real breakthroughs, including a hardware emulator capable of handling up to one-billion application specific integrated circuit (ASIC) gates.

The popularity of tools such as emulation for hardware/software co-verification has never been stronger. That’s because designers implementing System-on-Chip (SoC) devices must be able to simultaneously verify the correctness of both hardware and embedded software. This is especially true as software becomes a key product differentiator, the time to market compresses yet again and design sizes are hitting the one-billion ASIC gates threshold – unthinkable numbers not all that long ago.

It’s also true that coding the software part of an SoC consistently takes longer than it does to design the hardware, which has forced silicon vendors to wait for working silicon before software development begins. And, the fewer software applications written for a chip, the less likely the chip will be successful in the market. Therefore, achieving a working prototype for software development well in advance of silicon has become a top priority.

That’s why hardware/software co-verification tools have given hardware designers and software developers a reason to cheer. They give these teams with different skill sets a way to effectively communicate and work together, a far cry from the hardware-centric tools supporting hardware designers only that EDA consistently churned out until recently. Design teams view this shift as a welcome change since the SoC methodology combines software and hardware to form a complete system.

Recent enhancements in emulation technology are enabling the handling of one-billion ASIC gate designs at execution speed of multi-megahertz. That means that they are able to process billions of verification cycles – the ability to boot an OS like Linux, for instance – in few minutes.

These powerful "bug busting" emulators can imitate real hardware behavior, essential to firmware integration, and track the behavior of internal hardware signals. They can link a software debugger to the hardware debugger for tracing a software bug in the hardware domain and vice versa. And, emulators can act as a self-contained ASIC prototype driven by embedded testbenches, by a virtual software electronic system level (ESL) model or by an actual target system. They can achieve all of the above at a higher performance rate than traditional emulators, effectively performing both hardware verification and embedded software validation of very complex and very large SoCs.

Hardware emulators able to handle one-billion ASIC gates can shorten time to tapeout, improve product quality and eliminate costly re-spins, while reducing software development time ahead of silicon of the most complex SoC ever designed. More important, they are less expensive than traditional emulation, easier to use and flexible enough for a current project or the next one. Finally, hardware designers and software developers at last can share the same system and design representations.

After years discussing co-verification strategies with hundreds of design teams worldwide, I’m happy to report that there are solutions to managing the billion-gate design challenge. I invite you to walk the DAC Exhibit Floor and be pleasantly surprised by what you may find in the way of new tools and methodologies to solve your toughest co-verification problems. Stop by the EVE booth (#908, South Hall) to see firsthand how we broke the billion-gate barrier with ZeBu-Server, scalable and affordable emulation.

Source: http://www.chipdesignmag.com/display.php?articleId=3488